Neural network hardware acceleration: Leveraging parallelism in FPGAs to improve neural network performance
Date
2020-06-08
Authors
Lee, Robert
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Abstract
In many of today’s leading-edge computer vision research areas, the speed and resilience of artificial neural networks is vital to the system’s performance. Often, real-time processing may be necessary. However, due to its inherent computational complexity, it is difficult for purely software-based systems to meet real-time requirements. In this project, an FPGA-based implementation of a convolutional neural network hardware accelerator and its corresponding potentials for parallelism, low power, and reconfigurability are investigated.
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Keywords
Artificial neural network, convolutional neural network, CNN, Field Programmable Gate Array, FPGA, hardware acceleration, parallelism, reprogram, optimization, hardware description language