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Extended architectural enhancements for minimizing message delivery latency on cache-less architectures (e.g., Cell BE)

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dc.contributor.author Kroeker, Anthony
dc.date.accessioned 2012-01-12T23:43:09Z
dc.date.available 2012-01-12T23:43:09Z
dc.date.copyright 2011 en_US
dc.date.issued 2012-01-12
dc.identifier.uri http://hdl.handle.net/1828/3813
dc.description.abstract This thesis proposes to reduce the latency of MPI receive operations on cacheless architectures, by removing the delay of copying messages when they are first received. This is achieved by copying the messages directly into buffers in the lowest level of the memory hierarchy (e.g., scratchpad memory). The previously proposed solution introduced an Indirection Cache which would map between the receive variables and the buffered message payload locations. This proved somewhat beneficial, but the lookup penalty of the Indirection Cache limited its effectiveness. Therefore this thesis proposes that a most recently used buffer (i.e., an Indirection Buffer) be placed in front of the Indirection Cache to eliminate this penalty and speed up access. The tests conducted demonstrated that this method was indeed effective and improved over the original method by at least an order of magnitude. Finally, examination of implementation feasibility showed that this could be implemented with a small Cache, and that even with access times 6x slower than initially assumed, the approach with the Indirection Buffer would still be effective. en_US
dc.language English eng
dc.language.iso en en_US
dc.subject computer engineering en_US
dc.subject computer architecture en_US
dc.subject cell processor en_US
dc.subject mpi en_US
dc.subject cache injection en_US
dc.subject cacheless en_US
dc.subject Indirection Cache en_US
dc.subject Indirection Buffer en_US
dc.title Extended architectural enhancements for minimizing message delivery latency on cache-less architectures (e.g., Cell BE) en_US
dc.type Thesis en_US
dc.contributor.supervisor Dimopoulos, Nikitas J.
dc.degree.department Dept. of Electrical and Computer Engineering en_US
dc.degree.level Master of Applied Science M.A.Sc. en_US
dc.rights.temp Available to the World Wide Web en_US
dc.description.scholarlevel Graduate en_US


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