On Kalman filter implementation on FPGAs

Date

2012-12-17

Authors

Bhatia, Zorawar

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Abstract

The following dissertation attempts to highlight and address the implementation and performance of a Kalman filter on an FPGA. The reasons for choosing the Kalman filter and the platform for implementation are highlighted as well as an in depth explanation of the components and theory behind both are given. A controller system which allows the optimal performance of the Kalman filter on it is developed in VHDL. The design of the controller is dictated by the analysis of the Kalman filter which ensures only the most necessary components and operations are built into the instruction set. The controller is made up of several components including the loader, the ALU, Data RAM, KF IO, Control Store and the Branch Unit. The components working in conjunction allows the system to interface though a handshaking protocol with a peripheral of arbitrary latency. The control store is loaded with program code that is determined by converting human readable assembler into machine code through a Perl encoder. The controller system is tested and verified though an extensive testbench environment that emulates all outside signals and views internal operations. The controller system is capable of five matrix operations which are computed in parallel due to the FPGA development environment, which is far superior in this case to the alternative: a software solution, due to the vector operations inherent in the Kalman filter algorithm. The Kalman filter operation is analyzed and simulated in a MATLAB environment and this analysis confirms the need for the parallel processing power of the FPGA system upon which the controller has been built. FPGA statistical analysis confirms the successful implementation of the system meeting all criteria set at the outset of the project, including memory usage, IO usage and performance and accuracy benchmarks.

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Keywords

Kalman filter, FPGA, Assembler, Perl, VHDL, MATLAB, design, simulation

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