Advanced Encryption Standard Implementation on Field Programmable Gate Arrays

Abstract

Cryptography provides users with secure communications and data transmission privacy and authenticity (Coron, 2006). Today the most widely used algorithm for private key encryption is the Advanced Encryption Standard (AES). It operates on 128 bit blocks of data in the form of a 4£4 matrix of bytes called the state matrix. The encryption/ decryption process is performed on this matrix using key sizes of 128, 192 or 256 bits. The AES round operations include shift rows, mix columns, and sub bytes using finite field arithmetic. Numerous studies have been done on the AES cryptosystem focusing on design optimization in terms of the memory used in hardware implementation (Van Dyken & Delgado-Frias, 2010). The sub bytes operations dominates the hardware complexity of AES due to its non linearity. In this report, the AES hardware feasibility is improved by implementing the sub bytes operation using inversion in GF(256). This inversion is decomposed into a network of logic gates which reduces the required read onlymemory (ROM) by 89% compared to using look up tables.