Advanced Encryption Standard Implementation on Field Programmable Gate Arrays

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dc.contributor.author Behrouzinekoo, Maryam
dc.date.accessioned 2017-12-05T23:12:49Z
dc.date.available 2017-12-05T23:12:49Z
dc.date.copyright 2017 en_US
dc.date.issued 2017-12-05
dc.identifier.uri http://hdl.handle.net/1828/8835
dc.description.abstract Cryptography provides users with secure communications and data transmission privacy and authenticity (Coron, 2006). Today the most widely used algorithm for private key encryption is the Advanced Encryption Standard (AES). It operates on 128 bit blocks of data in the form of a 4£4 matrix of bytes called the state matrix. The encryption/ decryption process is performed on this matrix using key sizes of 128, 192 or 256 bits. The AES round operations include shift rows, mix columns, and sub bytes using finite field arithmetic. Numerous studies have been done on the AES cryptosystem focusing on design optimization in terms of the memory used in hardware implementation (Van Dyken & Delgado-Frias, 2010). The sub bytes operations dominates the hardware complexity of AES due to its non linearity. In this report, the AES hardware feasibility is improved by implementing the sub bytes operation using inversion in GF(256). This inversion is decomposed into a network of logic gates which reduces the required read onlymemory (ROM) by 89% compared to using look up tables. en_US
dc.language.iso en en_US
dc.rights Available to the World Wide Web en_US
dc.subject Advanced Encryption Standard en_US
dc.subject AES en_US
dc.subject FPGA en_US
dc.subject sub bytes en_US
dc.subject ROM en_US
dc.title Advanced Encryption Standard Implementation on Field Programmable Gate Arrays en_US
dc.type project en_US
dc.contributor.supervisor Gulliver, T. Aaron
dc.degree.department Department of Electrical and Computer Engineering en_US
dc.degree.level Master of Engineering M.Eng. en_US
dc.description.scholarlevel Graduate en_US

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