Word-serial unified and scalable semi-systolic processor for field multiplication and squaring
Date
2021
Authors
Ibrahim, Atef
Journal Title
Journal ISSN
Volume Title
Publisher
Alexandria Engineering Journal
Abstract
This paper exhibits a word-serial unified and scalable semi-systolic processor core for concurrently executing both multiplication and squaring operations over GF(). The processor is extracted by applying a chosen non-linear scheduling and projection functions to the dependency graph of the adopted bipartite multiplication-squaring algorithm. It has the advantage of sharing the data-path resources between the two operations leading to considerable savings in both space and power resources. Also, the processor’s scalability nature provides the designer with higher flexibility to manage the processor size as well as its execution time. The acquired ASIC synthesis results of the explored word-serial multiplier-squarer architecture and the reported competing word-serial multiplier architectures indicate that the developed design significantly outperforms the competing ones in terms of area and consumed energy at the word-size of 32-bits. Therefore, the explored architecture is more suited for realizing cryptographic primitives in all resource-constrained embedded applications operating at this word-size.
Description
Keywords
Word-serial systolic/semi-systolic arrays, Cryptographic processors, Finite-field arithmetic, Resource-constrained embedded applications, Hardware security
Citation
Ibrahim, A. (2021). Word-serial unified and scalable semi-systolic processor for field multiplication and squaring. Alexandria Engineering Journal, 60(1), 1379- 1388. https://doi.org/10.1016/j.aej.2020.10.058.