Speed Comparison of Binary Adders Techniques

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dc.contributor.author Alghamdi, Abdulmajeed
dc.date.accessioned 2015-12-23T02:11:24Z
dc.date.available 2015-12-23T02:11:24Z
dc.date.copyright 2015 en_US
dc.date.issued 2015-12-22
dc.identifier.uri http://hdl.handle.net/1828/6986
dc.description.abstract The search for developing techniques of a digital circuit that assist in minimizing the challenges that occur nowadays in microelectronics is continuous. Arithmetic circuits especially adder target of a continues e effort that presents an interesting research field. Since adder occupies a critical position in arithmetic circuits design, it is important to ensure that the performance of adder meets certain specifications. In this report, we introduce different fast adders topologies with focus on computation speed parameter. In addition, we provide delay modeling and simulation of the fast adders to check their performance using Matlab software environment. The main goal is to provide a comprehensive review of fast adders and some new techniques that have been applied to improve their performance. en_US
dc.language.iso en en_US
dc.rights Available to the World Wide Web en_US
dc.title Speed Comparison of Binary Adders Techniques en_US
dc.type project en_US
dc.contributor.supervisor Gebali, Fayez
dc.degree.department Department of Electrical and Computer Engineering en_US
dc.degree.level Master of Engineering M.Eng. en_US
dc.description.scholarlevel Graduate en_US

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