Circuit blocks design for a current-mode CMOS image sensor chip




Wang, Xingming

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This thesis presents the design and implementation of a current-mode computational CMOS image sensor that performs video image compression based on the CRVDC (conditional replenishment video data compression) algorithm. With such on-chip pre-processing, a compression ratio of 10:1 can be achieved without significant signal degradation. Our research focuses on designing the basic building blocks. As the image sensor works in the current-mode, the building blocks will be current mirrors and current comparators. Several kinds of current mirrors have been analyzed in details and an improved regulated cascode current mirror was chosen. Through simulations and prototyping, we demonstrated that this current mirror is capable of achieving a resolution of 11 bits at 200MHz. To implement the CRVDC algorithm, it was necessary to design an accurate and fast current comparator. Two novel CMOS current comparators were proposed and analyzed and the results were compared to conventional CMOS current comparators. Simulations and measurements demonstrated that the new CMOS current comparators had better performance both in terms of the propagation delay and power dissipation. For the CMOS image sensor, a photodiode-type active pixel transducer was used to convert incident light to photocurrent. The characterization and modeling of the transducer were presented and detailed analyses on the performance was obtained from chips fabricated using the standard 0.18μm CMOS process technology. Since the electrical characteristics of the active devices in the pixel sensor chip can generate large fixed pattern noise (FPN), a current-mode FPN suppression circuit was designed and adopted. Based on the test results obtained from a fabricated prototype chip, a FPN suppression rate of 0.35% was achieved. An on-chip analog to digital converter (ADC) was necessary to implement digital interface and a current-mode pipeline ADC with 8 bit resolution was proposed. Simulation results demonstrated that the ADC was monotonic and possessed an integral nonlinearity (INL) of ±0.45 LSB and a differential nonlinearity (DNL) of ±0.43 LSB. Our results suggested that the overall design can more than adequately meet the system specifications of the computational CMOS image sensor and potentially can be used as a front-end processing block in other image processing applications such as in motion detection and in image segmentation for a dynamic environment.



Circuit design, Image sensor