Iaderoza, Beatriz Chiavegatto2010-02-262010-02-2620062010-02-26http://hdl.handle.net/1828/2277A reprogrammable hardware platform is used for the Co-design and implementation of a computationally intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)). The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software Co-design methodologies and techniques, and it is designed, implemented and evaluated on two distinct platforms, not simply by simulations. FPGAs are used as part of the reconfigurable hardware in both a PCI-based environment and in a more successful System-on-Chip (SOC) platform, which takes advantage of the closely-coupled interconnection between the hardware and software, thus minimizing the communication overhead. The case study, findings and general analysis lead to a possible ideal architecture for future approaches. Moreover, a more general detailed strategy can be seen for the transformation from software to a Co-design paradigm, maximizing parallelism.enAvailable to the World Wide Webembedded computer systemssystem designUVic Subject Index::Sciences and Engineering::Applied Sciences::Computer scienceThesis