Dravnieks, Olaf Olgert Walter2024-08-132024-08-1319921992https://hdl.handle.net/1828/17650In this thesis, logic cell array designs for a (31, k) Reed-Solomon Codec are examined. The normal basis and a power basis representation for GF(25) are considered with respect to the number of clock cycles and number of logical gates or configurable logic blocks required to implement Galois field addition, multiplication and inversion. The decoder is partitioned into 5 logical modules. Pipelining options for the 5 logical modules are considered, in light of the resulting speed and hardware requirements. Two methods of passing information between the modules are considered: direct passing of information, and using external memory to store each modules results. A software implementation of the (31, k) codec in the C programming language, and a Xilinx XC3000 Series PGA design for a 5 stage external RAM based decoder are presented.162 pagesAvailable to the World Wide WebUN SDG 7: Affordable and Clean EnergyThesis