Simulating NoC Mesh and Torus Topologies
| dc.contributor.author | Khan, Muhammad Ahsan | |
| dc.contributor.supervisor | Gebali, Fayez | |
| dc.date.accessioned | 2024-03-15T00:48:30Z | |
| dc.date.available | 2024-03-15T00:48:30Z | |
| dc.date.issued | 2017 | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Master of Engineering MEng | |
| dc.description.abstract | An interconnection network is a programmable system that transports the data between the terminals. The interconnection is important because of the limiting factor in the performance of many systems. Network on chip (NoC) plays a vital role in the memory latency or memory bandwidth, which are the two key performances in computer systems. Apart from them the topologies are also one of the most important performance factors. In this project the two most signi cant topologies, mesh topology and torus topology are studied. A study is conducted on the above two mentioned topologies by injecting various it rates with di erent combinations of virtual channels. The main objective of this project is to explain how virtual channels are e ective on throughput and latency on di erent topologies. The comparative evaluation of topologies will help to explore more features in detail which will be helping in future developing in NoC. | |
| dc.description.scholarlevel | Graduate | |
| dc.identifier.uri | https://hdl.handle.net/1828/7820 | |
| dc.language.iso | en | |
| dc.rights | Available to the World Wide Web | |
| dc.subject | Booksim | |
| dc.subject | NoC | |
| dc.subject | 2D Mesh Topology | |
| dc.subject | Mesh vs Torus topology | |
| dc.title | Simulating NoC Mesh and Torus Topologies | |
| dc.type | project |