FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for High-Performance Processor

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dc.contributor.authorHajkazemi, Mohammad Hossein
dc.contributor.supervisorBaniasadi, Amirali
dc.date.accessioned2013-08-20T20:14:55Z
dc.date.available2013-08-20T20:14:55Z
dc.date.copyright2013en_US
dc.date.issued2013-08-20
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en_US
dc.description.abstractThis thesis introduces an alternative Fault-Tolerant Power-Aware Hybrid Adder (or simply FARHAD) for high-performance processors. FARHAD, similar to earlier studies, relies on performing add operations twice to detect errors. Unlike previous studies, FARHAD uses an aggressive adder to produce the initial outcome and a low-power adder to generate the second outcome, referred to as the checker. FARHAD uses checkpoints, a feature already available to high-performance processors, to recover from errors. FARHAD achieves the high energy-efficiency of time-redundant solutions and the high performance of resource-redundant adders. We evaluate FARHAD from power and performance points of view using a subset of SPEC’2K benchmarks. Our evaluations show that FARHAD outperforms an alternative time-redundant solution by 20%. FARHAD reduces the power dissipation of an alternative resource-redundant adder by 40% while maintaining performance.en_US
dc.description.proquestcode0544en_US
dc.description.scholarlevelGraduateen_US
dc.identifier.urihttp://hdl.handle.net/1828/4802
dc.languageEnglisheng
dc.language.isoenen_US
dc.rights.tempAvailable to the World Wide Weben_US
dc.subjectfault-tolerant adderen_US
dc.subjectmodular redundancyen_US
dc.subjecttime redundancyen_US
dc.subjectlow-power adderen_US
dc.titleFARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for High-Performance Processoren_US
dc.typeThesisen_US

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