System-level design of power efficient FSMD architectures
| dc.contributor.author | Agarwal, Nainesh | |
| dc.contributor.supervisor | Dimopoulos, Nikitas J. | |
| dc.date.accessioned | 2009-05-06T17:37:28Z | |
| dc.date.available | 2009-05-06T17:37:28Z | |
| dc.date.copyright | 2009 | en |
| dc.date.issued | 2009-05-06T17:37:28Z | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Doctor of Philosophy Ph.D. | en |
| dc.description.abstract | Power dissipation in CMOS circuits is of growing concern as the computational requirements of portable, battery operated devices increases. The ability to easily develop application specific circuits, rather than program general-purpose architectures can provide tremendous power savings. To this end, we present a design platform for rapidly developing power efficient hardware architectures starting at a system level. This high level VLSI design platform, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time and power dissipation. We compare the CoDeL platform to a modern DSP and find that the CoDeL platform produces designs with somewhat slower run times but dramatically lower power dissipation. The CoDeL compiler produces an FSMD (Finite State Machine with Datapath) implementation of the circuit. This regular structure can be exploited to further reduce power through various techniques. To reduce dynamic power dissipation in the resulting architecture, the CoDeL compiler automatically inserts clock gating for registers. Power analysis shows that CoDeL's automated, high-level clock gating provides considerably more power savings than existing automated clock gating tools. To reduce static power, we use the CoDeL platform to analyze the potential and performance impact of power gating individual registers. We propose a static gating method, with very low area overhead, which uses the information available to the CoDeL compiler to predict, at compile time, when the registers can be powered off and powered on. Static branch prediction is used to more intelligently traverse the finite state machine description of the circuit to discover gating opportunities. Using simulation and estimation, we find that CoDeL with backward branch prediction gives the best overall combination of gating potential and performance. Compared to a dynamic time-based technique, this method gives dramatically more power savings, without any additional performance loss. Finally, we propose techniques to efficiently partition a FSMD using Integer Linear Programming and a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve considerable power savings since only one processor is active at any given time. Implementation and estimation shows that significant power savings can be expected, when the original machine is partitioned into two or more submachines. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Using CoDeL to rapidly prototype network processsor extensions. In SAMOS IV: International Symposium on Systems, Architectures, Modeling and Simulation, pages 333-342, November 2004. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Power efficient rapid system prototyping using CoDeL: The 2D DWT using lifting. In PacRim 2005: IEEE Pacific Rim Conference on Communications, Computers and signal Processing, pages 550-553, August 2005. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Rapidly prototyping DSP extensions using CoDeL: the DWT using lifting. In CCECE 2005: Canadian Conference on Electrical and Computer Engineering, pages 802-805, May 2005. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. E_cient automated clock gating using CoDeL. In SAMOS VI: International Symposium on Systems, Architectures, Modeling and Simulation, pages 79-88, July 2006. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Power e_cient rapid hardware development using codel and automated clock gating. In ISCAS 2006: IEEE International Symposium on Circuits and Systems, pages 5310-5313, May 2006. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Automated power gating of registers using CoDeL and FSM branch prediction. In SAMOS VII: International Symposium on Systems, Architectures, Modeling and Simulation, pages 294-303, July 2007. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. A DSPstone benchmark of CoDeL's automated clock gating platform. In ISVLSI 2007: IEEE Computer Society Annual Symposium on VLSI, pages 508-509, March 2007. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. High level FSMD design and automated clock gating using CoDeL. In PacRim 2007: IEEE Pacific Rim Conference on Communications, Computers and signal Processing, August 2007. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Towards automated power gating of registers using CoDeL. In ISCAS 2007: IEEE International Symposium on Circuits and Systems, pages 1629-1632, May 2007. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. FSMD partitioning for low power using ILP. In ISVLSI 2008: IEEE Computer Society Annual Symposium on VLSI, pages 63-68, April 2008. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. FSMD partitioning for low power using simulated annealing. In ISCAS 2008: IEEE International Symposium on Circuits and Systems, pages 1244-1247, May 2008. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. High-level FSMD design and automated clock gating with CoDeL. Canadian Journal of Electrical and Computer Engineering, 33(1):31-38, Winter 2008. | en |
| dc.identifier.bibliographicCitation | N. Agarwal and N. Dimopoulos. Towards automated FSMD partitioning for low power using simulated annealing. In SAMOS IX: International Symposium on Systems, Architectures, Modeling and Simulation, July 2009. | en |
| dc.identifier.uri | http://hdl.handle.net/1828/1405 | |
| dc.language | English | eng |
| dc.language.iso | en | en |
| dc.rights | Available to the World Wide Web | en |
| dc.subject | System-Level | en |
| dc.subject | VLSI | en |
| dc.subject | Power | en |
| dc.subject | CAD | en |
| dc.subject | FSMD | en |
| dc.subject | Hardware | en |
| dc.subject | High-level synthesis | en |
| dc.subject | clock gating | en |
| dc.subject | power gating | en |
| dc.subject | partitioning | en |
| dc.subject | CoDeL | en |
| dc.subject | Simulated Annealing | en |
| dc.subject | ILP | en |
| dc.subject | ESL | en |
| dc.subject.lcsh | UVic Subject Index::Sciences and Engineering::Engineering::Electrical engineering | en |
| dc.subject.lcsh | UVic Subject Index::Sciences and Engineering::Applied Sciences::Computer science | en |
| dc.title | System-level design of power efficient FSMD architectures | en |
| dc.type | Thesis | en |