Implementation of Frequency Divider by Ring Counter with Design Constraint based on FPGA
| dc.contributor.author | Li, Wenpei | |
| dc.contributor.supervisor | Sima, Mihai | |
| dc.contributor.supervisor | McGuire, Michael | |
| dc.date.accessioned | 2024-05-31T17:22:05Z | |
| dc.date.available | 2024-05-31T17:22:05Z | |
| dc.date.issued | 2024 | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Master of Engineering MEng | |
| dc.description.abstract | Shift registers have been widely used in the field of integrated circuits, which can be used to transport data from a flip-flop to another. A ring counter is composed of a shift register by connecting the input and output of it to form a ring. In this project, a type of frequency divider is implemented with a ring counter to divide the frequency of the clock, and its optimization can be achieved by timing constraints, placement constraints, and routing constraints. In this simulation, Xilinx Vivado is utilized as an optimization tool to refine the timing results of frequency divider, whereas the setup slack time and hold slack time are used as important references. The timing results measure the quality of the design at different stages of adding constraints and other modifications and optimizations are made based on them. All the constraints are completed by adding constraint files in the source except that the routing design should be done by the router tool in Vivado to choose better net nodes for the critical path. After the modification of all constraints, it shows an improvement in the design timing summary. | |
| dc.description.scholarlevel | Graduate | |
| dc.identifier.uri | https://hdl.handle.net/1828/16583 | |
| dc.language.iso | en | |
| dc.rights | Available to the World Wide Web | |
| dc.subject | constraint | |
| dc.subject | FPGA | |
| dc.subject | timing analysis | |
| dc.subject | placement | |
| dc.subject | routing | |
| dc.title | Implementation of Frequency Divider by Ring Counter with Design Constraint based on FPGA | |
| dc.type | project |