Multi-clock pipeline architecture for the IEEE 802.11a baseband transceiver

Date

2010-04-12T20:01:50Z

Authors

Mizani, Maryam

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

Demand for Wireless Local Area Networking (WLAN) has grown significantly during the past several years. WLAN systems need to support varying data rate applications and consume low amount of energy. This work presents a reconfigurable WLAN transceiver architecture that has the following key features: Four-stage pipeline struc¬ture to increase throughput and reduce dynamic power consumption; Multiple adjustable clocks to avoid excessive handshaking and buffering between pipeline stages, Dynamic reconfigurability to support different modes of operation; and Low reconfiguration cost, in terms of energy consumption and delay, to allow for efficient frame-by-frame adaptation. We have chosen the IEEE 802.11a standard as the demonstration platform, how-ever our ideas are extendable to other WLAN standards that are based on similar communication principles. For example, the popular IEEE 802.11g standard uses the same Orthogonal Frequency Division Multiplexing (OFDM) scheme as 802.11a. Consequently, both standards require somewhat similar data processing; i.e., our design techniques remain applicable. Our proposed architecture is prototyped on Xilinx FPGA, and simulations show a relatively low power consumption in comparison with other 802.11a baseband processors.

Description

Keywords

Wireless communication, Baseband, WLAN

Citation