VLSI implementation of a router for the backtrack-to-the-origin-and-retry-routing scheme of the hypercycle based interconnection networks
| dc.contributor.author | Radhakrishnan, Sivakumar | en_US |
| dc.date.accessioned | 2024-08-15T17:36:52Z | |
| dc.date.available | 2024-08-15T17:36:52Z | |
| dc.date.copyright | 1991 | en_US |
| dc.date.issued | 1991 | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Master of Applied Science M.A.Sc. | en |
| dc.description.abstract | Hypercycles are a new class of multidimensional graphs that are ideal vehicles for designing interconnection networks for distributed systems. Hypercycle graphs are generalizations of n-cube and they offer simple, elegant and efficient routing among the different nodes of the network. Hypercycles embody a cyclic interconnection topology and have the ability, given a fixed degree, to form a number of alternate size graphs. This property can be tailored to meet the required application resulting in an efficient utilization of the network. The regular structure of a Hypercycle allows the implementation of simple routing algorithms which require no detailed knowledge of the network interconnection. The Backtrack-to-the-origin-and-retry-routing scheme (BTOR) considered here is one of the several types of routing strategies that can be implemented in Hypercycle networks. The basic tenet of the BTOR scheme is to perform the routing by choosing at random , one of the available paths from each intermediate node that are at shortest d istances from the source to the destination. If a path is blocked at some stage in the network, the routing is collapsed back to the origin for retry. The BTOR scheme is controlled by a routing engine present in each node of the network. In this thesis, the theory, design and hardware realization of the proposed router are presented. The designs which have evolved as part of this research have been fabricated in the 1.2 µ and 3 µ CMOS technologies and the prototypes have been tested and verified. | |
| dc.format.extent | 230 pages | |
| dc.identifier.uri | https://hdl.handle.net/1828/19416 | |
| dc.rights | Available to the World Wide Web | en_US |
| dc.title | VLSI implementation of a router for the backtrack-to-the-origin-and-retry-routing scheme of the hypercycle based interconnection networks | en_US |
| dc.type | Thesis | en_US |
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