The UARx (Universal Asynchronous Receiver-Serial to Parallel Converter)
| dc.contributor.author | Phukan, Jahnabi | |
| dc.contributor.supervisor | Gebali, Fayez | |
| dc.contributor.supervisor | Li, Kin. Fun. | |
| dc.date.accessioned | 2016-01-04T18:13:05Z | |
| dc.date.available | 2016-01-04T18:13:05Z | |
| dc.date.copyright | 2015 | en_US |
| dc.date.issued | 2016-01-04 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Engineering M.Eng. | en_US |
| dc.description.abstract | Universal Asynchronous Receiver Transmitter (UART) is a full duplex receiver/transmitter. It is a microchip with programming that controls a computer’s interface to its attached serial devices and is widely used in data communication process especially for its advantages of high reliability, long distance and low cost. This project is specifically about the receiver (UARx) design that consists of two modules: bit-ASCII module and ASCII-word module. Each module specifies the function of their own individual sub-module. The bit-ASCII module, once detected the start bit, collects each bit serially and converts it to a valid ASCII character. After the conversion, each ASCII character is transferred to the ASCII-word module. The whole design provides non-clocked serial communications between two devices. The receiver logic implementation can be set up at different baud rates using a 50hz clock. All modules are designed and synthesized in VHDL and the reliability of VHDL implementation of the UARx is verified by simulated waveforms using Xilinx ISE 13.4 tool for simulation and synthesis. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/7002 | |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | UART | en_US |
| dc.title | The UARx (Universal Asynchronous Receiver-Serial to Parallel Converter) | en_US |
| dc.type | project | en_US |