Variable ordering for ROBDD-based FPGA logic synthesis
| dc.contributor.author | Crow, Jacqueline Elsie | en_US |
| dc.date.accessioned | 2024-08-13T18:16:37Z | |
| dc.date.available | 2024-08-13T18:16:37Z | |
| dc.date.copyright | 1995 | en_US |
| dc.date.issued | 1995 | |
| dc.degree.department | Department of Computer Science | |
| dc.degree.level | Master of Science M.Sc. | en |
| dc.description.abstract | The FPGA is becoming a more and more popular replacement for ASICs. Logic synthesis techniques for this technology have been adopted and modified from those used for regular ASICs. In this thesis, a technique using ROBDDs for logic synthesis for LUT-based FPGAs is investigated. The ROBDD is a useful representation for logic functions as it is a canonical form and it is relatively straight-forward to map this form to LUT-based FPGAs. A major problem with this representation, however, is that the variable ordering can have a very large effect on the size of the ROBDD. Another way of representing a function is with its autocorrelation coefficients. These provide information about areas of similarity in a function. This thesis presents methods of variable ordering for ROBDDs based on the autocorrelation coefficients of the function. The questions we investigate are whether this method of ordering consistently produces ROBDDs of a reasonable size, and whether these ROBDDs can be mapped to LUT-based FPGAs to result in a smaller number of logic blocks than on average. | |
| dc.format.extent | 159 pages | |
| dc.identifier.uri | https://hdl.handle.net/1828/17568 | |
| dc.rights | Available to the World Wide Web | en_US |
| dc.title | Variable ordering for ROBDD-based FPGA logic synthesis | en_US |
| dc.type | Thesis | en_US |
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