A Modified Minimal Gated Unit and Its FPGA Implementation
| dc.contributor.author | Zhu, Tong Jr | |
| dc.contributor.supervisor | Dong, Xiao Dai Jr | |
| dc.date.accessioned | 2020-12-24T23:28:42Z | |
| dc.date.available | 2020-12-24T23:28:42Z | |
| dc.date.copyright | 2020 | en_US |
| dc.date.issued | 2020-12-24 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Engineering M.Eng. | en_US |
| dc.description.abstract | Recurrent neural networks (RNNs) are versatile structures used in a variety of sequence data-related applications. The two most popular proposals are long short-term memory (LSTM) and gated recurrent unit (GRU) networks. Towards the goal of building a simpler and more efficient network, minimal gated unit (MGU) has appeared and shown quite promising results. In this project, we present a simple and improved MGU model, MGU\_1, implemented on scalable field programmable gate arrays (FPGA). Experiments with various sequence data show that the MGU\_1 has better accuracy compared to the MGU. The accelerator implemented on FPGA accelerates the inference phase utilizing the model trained on our indoor localization data set. It has two layers of MGU\_1 and each has 32 hidden units. The accelerator can achieve 142 MHz and 60 GOPS on the Xilinx XC7Z020 FPGA and outperforms the Intel i5-5350U based software solution by two orders of magnitude. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/12500 | |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | RNN | en_US |
| dc.subject | FPGA | en_US |
| dc.subject | MGU | en_US |
| dc.subject | Indoor Localization | en_US |
| dc.title | A Modified Minimal Gated Unit and Its FPGA Implementation | en_US |
| dc.type | project | en_US |