VHDL design of an ATM switch

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dc.contributor.authorGilderson, James Andrewen_US
dc.date.accessioned2024-08-13T22:54:52Z
dc.date.available2024-08-13T22:54:52Z
dc.date.copyright1995en_US
dc.date.issued1995
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en
dc.description.abstractThe next generation of communication networks will combine all forms of traffic on one universal network infrastructure. The Asynchronous Transfer Mode (ATM) has been proposed for this infrastructure. However, there still exist many unresolved issues in imple­menting a full ATM network. This thesis examines how to integrate the different cell flows found in ATM networks into one hardware architecture within an ATM switch while pro­viding the necessary functionality to route cells and manage the network resources. The general requirements of an ATM switch are presented based on ATM standards documents, and these requirements are used to describe an ATM switch as a set of compo­nents using a structured VLSI design methodology. This description is used to develop a modular design for an ATM Layer switch that incorporates all three planes of the ATM Pro­tocol Model as well as other necessary functions. A survey of current ATM switching fabrics is also presented to examine the switching mechanism and how input and output processors can be added to the fabric to provide a full ATM switch implementation. Based on the modular ATM switch design, the survey of switching fabrics, and other implementation issues, an ATM switch was implemented using high-level VHDL model­ling. This implementation provides many of the ATM switch functions while providing for the integration of software-based modules for signalling and management processors. This ATM switch implementation provides a simple architecture for a local area switch using a TDM bus switching fabric in conjunction with combined input-output buffering. The archi­tecture supports eight classes of user cells in addition to signalling, OAM and ILMI cells, each of which are serviced using a priority queuing mechanism at the output ports. Multi­casting is supported, as is cell tagging and selective cell discard. The logic of this VHDL model has been verified through simulation, and the cell flow between the modules within the switch has been examined through a study of bus arbitration mechanisms and conten­tion resolution. This design is highly modular, providing the means for simple design changes and the use of a variety of switching fabrics, and as such is a candidate for imple­mentation as a VLSI chipset.
dc.format.extent106 pages
dc.identifier.urihttps://hdl.handle.net/1828/17932
dc.rightsAvailable to the World Wide Weben_US
dc.titleVHDL design of an ATM switchen_US
dc.typeThesisen_US

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