Chip-level and reconfigurable hardware for data mining applications
| dc.contributor.author | Perera, Darshika Gimhani | |
| dc.contributor.supervisor | Li, Kin F. | |
| dc.date.accessioned | 2012-05-04T20:56:27Z | |
| dc.date.available | 2012-05-04T20:56:27Z | |
| dc.date.copyright | 2012 | en_US |
| dc.date.issued | 2012-05-04 | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Doctor of Philosophy Ph.D. | en_US |
| dc.description.abstract | From mid-2000s, the realm of portable and embedded computing has expanded to include a wide variety of applications. Data mining is one of the many applications that are becoming common on these devices. Many of today’s data mining applications are compute and/or data intensive, requiring more processing power than ever before, thus speed performance is a major issue. In addition, embedded devices have stringent area and power requirements. At the same time manufacturing cost and time-to-market are decreasing rapidly. To satisfy the constraints associated with these devices, and also to improve the speed performance, it is imperative to incorporate some special-purpose hardware into embedded system design. In some cases, reconfigurable hardware support is desirable to provide the flexibility required in the ever-changing application environment. Our main objective is to provide chip-level and reconfigurable hardware support for data mining applications in portable, handheld, and embedded devices. We focus on the most widely used data mining tasks, clustering and classification. Our investigation on the hardware design and implementation of similarity computation (an important step in clustering/classification) illustrates that the chip-level hardware support for data mining operations is indeed a feasible and a worthwhile endeavour. Further performance gain is achieved with hardware optimizations such as parallel processing. To address the issue of limited hardware foot-print on portable and embedded devices, we investigate reconfigurable computing systems. We introduce dynamic reconfigurable hardware solutions for similarity computation using a multiplexer-based approach, and for principal component analysis (another important step in clustering/classification) using partial reconfiguration method. Experimental results are encouraging and show great potential in implementing data mining applications using reconfigurable platform. Finally, we formulate a design methodology for FPGA-based dynamic reconfigurable hardware, in order to select the most efficient FPGA-based reconfiguration method(s) for specific applications on portable and embedded devices. This design methodology can be generalized to other embedded applications and gives guidelines to the designer based on the computation model and characteristics of the application. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/3982 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights.temp | Available to the World Wide Web | en_US |
| dc.subject | portable | en_US |
| dc.subject | embedded | en_US |
| dc.subject | hardware | en_US |
| dc.subject | clustering | en_US |
| dc.subject | classification | en_US |
| dc.title | Chip-level and reconfigurable hardware for data mining applications | en_US |
| dc.type | Thesis | en_US |