High-level built-in self-testable synthesis of digital systems

Date

2010-01-26T17:24:29Z

Authors

Yang, Laurence Tianruo

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Abstract

Driven by the rapid growth of the Internet, communication technologies; pervasive computing, automobiles, airplanes, wireless and portable consumer electronics, Embedded Systems and Systems-on-Chip (SoC) have moved from a craft to an emerging and very promising discipline in today's electronic industry. Testing of a fabricated chip is a process that applies a sequence of inputs to the chip and analyzes the chip's output sequence to ascertain whether it functions correctly. As the chip density grows to beyond millions of gates, Embedded Systems and Systems-on-Chip testing becomes a formidable task. Vast amounts of time and money have been invested by the industry just to ensure the high testability of products. On the other hand, as design complexity drastically increases, current gate-level design and test methodology alone can no longer satisfy stringent time-to-market requirements. The High-Level Test Synthesis (HLTS) system, which this thesis mainly focuses on, is to develop new systematic techniques to integrate testability consideration, specially with Built-In Self-Test. (BIST) techniques into the synthesis process. It. makes it possible for an automatic synthesis tool to predict testability of the synthesized embedded systems or chips accurately in the early stage. It also optimizes the designs in terms of test cost as well as performance and hardware area cost.

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Keywords

integrated circuits, very large scale integration, testing

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