Network-on-Chip Turn-aware application mapping optimization using Reinforcement Learning




Shammasi, Mohammadmehdi

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In todays advanced SoCs (System-on-Chip), power efficiency is a crucial concern. As chips get denser and more complicated, power consumption is becoming the bottleneck in further enhancing system’s performance. Serving as the backbone for many-core chips, NoCs (Network-on-chip) consume a significant share of total chips power. As a result, decreasing the power consumption in these components can reduce the total chip’s power significantly. Power-gating is a promising technique which can be used to reduce the static power consumption in NoC’s routers. In this method routers are put in a sleep mode and only wake up when a turning packet needs to pass. Since the process of waking up the router takes several cycles to complete, turning packets will experience a high amount of latency. In this regard, application mapping has a significant impact on number of turns and latency between cores of an application. In this article we propose a Reinforcement Learning framework based on Actor-Critic architecture to optimize the application mapping problem for fewer number of turns as well as keeping the distance of the cores minimum. Our RL framework learns the heuristic of the mapping problem and outputs a sub-optimal mapping. A 2-opt local search algorithm fine-tunes this mapping and provides an improved mapping. The results of our simulations show that this RL framework could achieve better performance in terms of cost and algorithm run-time comparing to other heuristic algorithms such as Simulated Annealing (SA) and Genetic Algorithm (GA).



NOC, Network on chip, Application mapping, Reinforcement learning