PUF Evaluation Metrics on 7 Series FPGA: Comparative Analysis of Arbiter, XOR Arbiter, and Double Arbiter PUFs for Uniqueness, Randomness, and Stability
| dc.contributor.author | Lunagariya, janviben | |
| dc.contributor.supervisor | Sima, Mihai | |
| dc.contributor.supervisor | Papadopoulos, Chris | |
| dc.date.accessioned | 2024-01-23T20:57:27Z | |
| dc.date.available | 2024-01-23T20:57:27Z | |
| dc.date.copyright | 2024 | en_US |
| dc.date.issued | 2024-01-23 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Engineering M.Eng. | en_US |
| dc.description.abstract | Hardware security modules play a crucial role in protecting and preserving technologically integrated systems that are used in daily life. They employ cryptographic protocols to secure a system against adversaries. Generally, cryptographic algorithms and security keys are essential for maintaining the security of a system. Cryptography uses a secret key to encipher and decipher the data. The confidential keys are stored in a non-volatile memory, making it easily accessible to potential attackers.The hardware security primitive, Physical Unclonable Function (PUF) is a promising alternative for enhancing the security of interconnected devices. Physical Unclonable Functions are specialized circuit components that exploit the subtle variations inherent in microchip fabrication. These variances enable the creation of unique "fingerprint" output sequences, or responses, in reaction to specific inputs or challenges. The random, device-specific nature of these variations and their replication difficulty - even by the original manufacturer using identical methods, tools, and parameters - make PUFs an excellent choice for cryptographic key generation. Moreover, these characteristics are designed to remain unchanged, reinforcing their suitability for this application. The Arbiter-based Physically Unclonable Function (PUF) is a type of delay-based PUF that utilizes signal delay-line time differences. However, previous studies indicated that Arbiter PUF, when implemented on Xilinx Virtex-5 FPGAs, produced nearly identical responses by exhibiting low uniqueness. Other variants of Arbiter PUF, such as XOR Arbiter PUF and the Double Arbiter PUF, were introduced to address this issue. This novel technique generates highly unique responses from duplicated Arbiter PUFs on FPGAs at a comparable cost to the 2-XOR Arbiter PUF. The Double Arbiter PUF differs from the 2-XOR version in the mode of operation, particularly regarding wire assignment between the arbiter and the final selector output signals. This study evaluates these PUFs for uniqueness, randomness, and stability on Xilinx 7-series FPGA Devices and seeks to identify a new Arbiter PUF operation mode that is feasible for FPGA implementation. We propose the 3-1 Double Arbiter PUF, which includes an extra duplicated Arbiter PUF, yielding three Arbiter PUFs that produce a 1-bit response. When compared with the 3-XOR Arbiter PUF, the 3-1 Double Arbiter PUF shows better response uniqueness and randomness estimated at 50%, indicating that the evaluation metrices of the PUF can be improved by using a new Arbiter PUF operation mode. We show that we can improve uniqueness and randomness using the new mode of operation for the Arbiter PUF performance characteristics for 16, 32, and 64-bit selector pairs for 65,536 responses. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/15843 | |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Hardware security | en_US |
| dc.subject | Physical Unclonable Functions | en_US |
| dc.subject | FPGAs | en_US |
| dc.subject | Xilinx Vivado | en_US |
| dc.subject | XOR APUF | en_US |
| dc.subject | Double APUF | en_US |
| dc.subject | Randomness | en_US |
| dc.subject | Stability | en_US |
| dc.subject | Uniqueness | en_US |
| dc.subject | Verilog | en_US |
| dc.title | PUF Evaluation Metrics on 7 Series FPGA: Comparative Analysis of Arbiter, XOR Arbiter, and Double Arbiter PUFs for Uniqueness, Randomness, and Stability | en_US |
| dc.type | project | en_US |
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- We introduced a 3-1 DAPUF using three selector chains. Our evaluation using Artix-7 FPGA indicates that, compared to the traditional Arbiter PUF and 3-XOR APUF, the 3-1 DAPUF notably improves response uniqueness. Our demonstration will show how uniqueness can be enhanced by employing a novel operational mode for APUF and XORing responses from additional duplicated arbiter chains on Artix 7 FPGAs in Xilinx Vivado tool using post implementation timing simulation. By duplicating three APUF chains and introducing three selector chains of APUF, we increased the uniqueness, randomness and stability of APUF responses.
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