Switching element design for BISDN

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dc.contributor.authorMund, Graeme Braden_US
dc.date.accessioned2024-08-14T22:55:14Z
dc.date.available2024-08-14T22:55:14Z
dc.date.copyright1992en_US
dc.date.issued1992
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en
dc.description.abstractA general overview of interconnection networks is given. The delta network is chosen for the switch fabric of a Broad band ISDN ATM switch. Architectural options for the switching elements of a delta network are identified. Formulas are developed which analyze the throughput and delay performance of delta networks composed of switching elements based on these architectures. The formulas are more general than those found in the literature. Simulations are performed to validate the analysis. The optimum switching element architecture is chosen. A design is given for a 25 MHz CMOS 2 x 2 switching element capable of hand ling proposed Broadband ISDN data. rates of 155.520 Mbits/sec. Data.paths throughout the switching eleĀ­ment are nine bits wide, including a parity bit. With virtual cut-through enabled, a packet may exit a switching element as early as three clock cycles after entering the switching element.en
dc.format.extent141 pages
dc.identifier.urihttps://hdl.handle.net/1828/19075
dc.rightsAvailable to the World Wide Weben_US
dc.subjectUN SDG 9: Industry, Innovation, and Infrastructureen
dc.titleSwitching element design for BISDNen_US
dc.typeThesisen_US

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