A New design for testability methodology for sequential circuits
Date
1994
Authors
Costi, Claudio
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Abstract
In the last five years, ASIC (Application Specific Integrated Circuit) density and complexity have exploded while quality and quick turnaround have both become indispensable factors of the manufacturing process. The testing process, which consists of generating and applying tests to evaluate the quality of a product, accounts for nearly a third of the ASIC development cycle. Test generation for sequential circuits is a complex and computationally expensive activity. Design for testability (DFT) techniques are among the most popular techniques used to reduce the complexity of the testing process while achieving high fault coverage and quick turnaround.
This thesis introduces a new DFT methodology for sequential circuits based on an input/output pin utilization which exploits the possibility to observe and control internal lines. This new testing methodology is capable of detecting a high percentage of stuck-at faults within short test application time. The goal has been to reduce test application time while maintaining the same fault coverage as the one obtained using the full scan technique.
Two different automatic tools , which employ the new DFT technique, are proposed and their implementation is described. Referring to the standard ISCAS89 benchmark sequential circuits, both results from the literature and results obtained using a commercial automatic tool (the Test Compiler from Synopsys) are compared to the performances of the proposed methodology. Experiments show that the new methodology achieves high fault coverage while reducing the test application time.