Logic cell array designs for a (31,k) Reed-Solomon Codec

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dc.contributor.authorDravnieks, Olaf Olgert Walteren_US
dc.date.accessioned2024-08-13T20:18:46Z
dc.date.available2024-08-13T20:18:46Z
dc.date.copyright1992en_US
dc.date.issued1992
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en
dc.description.abstractIn this thesis, logic cell array designs for a (31, k) Reed-Solomon Codec are examined. The normal basis and a power basis representation for GF(25) are considered with respect to the number of clock cycles and number of logical gates or configurable logic blocks required to implement Galois field addition, multiplication and inversion. The decoder is partitioned into 5 logical modules. Pipelining options for the 5 logical modules are considered, in light of the resulting speed and hardware requirements. Two methods of passing information between the modules are considered: direct passing of information, and using external memory to store each modules results. A software implementation of the (31, k) codec in the C programming language, and a Xilinx XC3000 Series PGA design for a 5 stage external RAM based decoder are presented.en
dc.format.extent162 pages
dc.identifier.urihttps://hdl.handle.net/1828/17650
dc.rightsAvailable to the World Wide Weben_US
dc.subjectUN SDG 7: Affordable and Clean Energyen
dc.titleLogic cell array designs for a (31,k) Reed-Solomon Codecen_US
dc.typeThesisen_US

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