Processor allocation and message broadcasting in hypercycle interconnection networks
| dc.contributor.author | Dimakopoulos, Vassilios V. | en_US |
| dc.date.accessioned | 2024-08-13T20:18:41Z | |
| dc.date.available | 2024-08-13T20:18:41Z | |
| dc.date.copyright | 1992 | en_US |
| dc.date.issued | 1992 | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Master of Applied Science M.A.Sc. | en |
| dc.description.abstract | Hypercycles are a class of static multiprocessor interconnection networks with the ability of matching the processing node and communication link restrictions of a large number of applications. This is in contras t with other popular interconnection topologies including hypercubes, k-ary n-cubes and generalized hypercubes. The regular structure of hypercycles allows for simple routing strategies which are responsible for the communication between the processing nodes. Broadcasting a message to all the processors in the network is an essential part of the routing engine and an algorithm that implements it for hypercycles constitutes part of this thesis. The proposed algorithm is analysed and proven to be optimal. Processor allocation which is the second and most important subject of this study is a major issue for achieving high performance in multiprocessor systems. This theoretical problem has topology-specific solutions and various strategies to deal with it for the hypercycles case are presented here. Comparisons between the proposed strategies are made using both analytical and computer simulation tools. Part of this thesis was the implementation of a simulator to help with these comparisons. Hypercubes, being a subset of hypercycles , can benefit from the proposed strategies which exhibited better performance than the ones with similar complexity proposed in the current literature. | en |
| dc.format.extent | 155 pages | |
| dc.identifier.uri | https://hdl.handle.net/1828/17645 | |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | UN SDG 9: Industry, Innovation, and Infrastructure | en |
| dc.title | Processor allocation and message broadcasting in hypercycle interconnection networks | en_US |
| dc.type | Thesis | en_US |
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