Speed Comparison of Binary Adders Techniques

dc.contributor.authorAlghamdi, Abdulmajeed
dc.contributor.supervisorGebali, Fayez
dc.date.accessioned2015-12-23T02:11:24Z
dc.date.available2015-12-23T02:11:24Z
dc.date.copyright2015en_US
dc.date.issued2015-12-22
dc.degree.departmentDepartment of Electrical and Computer Engineeringen_US
dc.degree.levelMaster of Engineering M.Eng.en_US
dc.description.abstractThe search for developing techniques of a digital circuit that assist in minimizing the challenges that occur nowadays in microelectronics is continuous. Arithmetic circuits especially adder target of a continues e effort that presents an interesting research field. Since adder occupies a critical position in arithmetic circuits design, it is important to ensure that the performance of adder meets certain specifications. In this report, we introduce different fast adders topologies with focus on computation speed parameter. In addition, we provide delay modeling and simulation of the fast adders to check their performance using Matlab software environment. The main goal is to provide a comprehensive review of fast adders and some new techniques that have been applied to improve their performance.en_US
dc.description.scholarlevelGraduateen_US
dc.identifier.urihttp://hdl.handle.net/1828/6986
dc.language.isoenen_US
dc.rightsAvailable to the World Wide Weben_US
dc.titleSpeed Comparison of Binary Adders Techniquesen_US
dc.typeprojecten_US

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