Secured-by-design FPGA against side-channel attacks based on power consumption
| dc.contributor.author | Almohaimeed, Ziyad Mohammed | |
| dc.contributor.supervisor | Sima, Mihai | |
| dc.date.accessioned | 2017-08-31T19:00:25Z | |
| dc.date.copyright | 2017 | en_US |
| dc.date.issued | 2017-08-31 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Doctor of Philosophy Ph.D. | en_US |
| dc.description.abstract | Power Analysis Attacks pose serious threats to hardware implementations of cryptographic systems. To retrieve the secret key, the attackers can exploit the mutual information between power consumption and processed data / operations through monitoring the power consumption of the cryptosystems. Field Programmable Gate Arrays (FPGA) have emerged as attractive implementation platforms for providing hardware-like performance and software-like flexibility for cryptosystem developers. These features come at the expense of larger power consumption, which makes FPGAs more vulnerable to power attacks. Different countermeasures have been introduced in the literature, but as they have originally been developed for Application-Specific Integrated Circuits (ASIC), mapping them onto FPGAs degrades their effectiveness. In this work, we propose a logic family based on pass transistors, which essentially consists of hardware replication, that can be used to build FPGAs with constant power consumption. Since the power consumption is no longer related to processed data and operations, a quadruple robustness to attacks based on dynamic power consumption, static power consumption, glitches, and early evaluation effect is achieved. Such a secured-by-design FPGA will relieve the cryptosystems developers from doing advanced analog design to secure the cryptosystem implementation. Our pass-transistor logic family can also be used in implementing ASICs. The silicon area overhead costs are shown to be less than prior art, which makes our FPGA attractive to cryptosystems developers. | en_US |
| dc.description.embargo | 2018-07-26 | |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/8522 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Side-Channel Attacks | en_US |
| dc.subject | Power analysis attacks | en_US |
| dc.subject | Secured-by-Design FPGA | en_US |
| dc.subject | Differential Power Attacks | en_US |
| dc.subject | DPA | en_US |
| dc.subject | Correlation Power Attacks | en_US |
| dc.subject | CPA | en_US |
| dc.title | Secured-by-design FPGA against side-channel attacks based on power consumption | en_US |
| dc.type | Thesis | en_US |