Switching and error recovery in terabit ATM networks
| dc.contributor.author | Sabaa, Amr Gaber | |
| dc.contributor.supervisor | el Guibaly, Fayez H. F. | |
| dc.contributor.supervisor | Shpak, Dale John | |
| dc.date.accessioned | 2017-11-15T21:23:02Z | |
| dc.date.available | 2017-11-15T21:23:02Z | |
| dc.date.copyright | 1998 | en_US |
| dc.date.issued | 2017-11-15 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Doctor of Philosophy Ph.D. | en_US |
| dc.description.abstract | This thesis addresses two of the main issues required to build reliable terabit ATM networks. A high-capacity switch and an efficient error recovery protocol are the key elements in building a reliable terabit ATM network. In this thesis, a terabit switch architecture and a reliable end-to-end error recovery protocol for terabit networks are introduced. The proposed terabit ATM switch architecture is designed to work efficiently in low-capacity and high-capacity environments. The architecture is developed by interconnecting small-capacity switching modules in a scalable fashion. The switching module can be used alone as a small-capacity ATM switch. Multiple the switching modules can be used to achieve any required switching capacity. The proposed interconnecting scheme provides remarkable low cell-delay characteristics with a simple distributed cell scheduler. The proposed architecture has a high reliability: Even when a complete switching module fails the switch will continue to work efficiently. The switching element which is introduced as the main building block for the terabit switch architecture is a nonblocking input buffer ATM switch. The input buffers are implemented as groups of parallel shift-registers. The parallel nature of the storing buffers overcomes the Head Of Line and low throughput problems of existing input buffer switch architectures. In addition, using the shift registers overcomes the need for serial-to-parallel and parallel-to-serial format conversions. ATM networks support different types of services having different delay and loss requirements. A priority scheduling scheme is proposed to facilitate the support of different Qualities of Service. The proposed scheme satisfies both real-time and non-real-time service requirements. Cell loss is not acceptable for some data applications. This thesis proposes an efficient error recovery protocol which guarantees reliable communication with limited overhead. The proposed protocol requires a low number of control packets to achieve reliable communication. It also adapts itself, in order to work efficiently during both congested and non congested states. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/8798 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Computer networks | en_US |
| dc.subject | Asynchronous transfer mode | en_US |
| dc.subject | Integrated services digital networks | en_US |
| dc.title | Switching and error recovery in terabit ATM networks | en_US |
| dc.type | Thesis | en_US |