Content Addressable Memory (CAM) Implementation and Power Analysis on FPGA
| dc.contributor.author | Hu, Teng | |
| dc.contributor.supervisor | Sima, Mihai | |
| dc.contributor.supervisor | Papadopoulos, Chris | |
| dc.date.accessioned | 2017-02-22T17:17:17Z | |
| dc.date.available | 2017-02-22T17:17:17Z | |
| dc.date.copyright | 2017 | en_US |
| dc.date.issued | 2017-02-22 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Engineering M.Eng. | en_US |
| dc.description.abstract | Content Addressable Memory (CAM) has been widely used in network devices for fast lookup functions. CAM implementation based on Field Programmable Gate Array (FPGA) has become a popular solution due to its flexibility. With the increasing capacity of CAM, reducing power consumption has been the main challenge for implementation on FPGA. This report investigates and implements two low-power schemes, pipelining and precomputation for RAM-based CAM. The pipelining scheme divides RAM into several segments as a pipeline. Mismatched RAM blocks disable the subsequent search operation in the following segments and therefore power consumption is reduced. For precomputation scheme, extra information is extracted from CAM words and input keys before the search operation. It saves power by filtering out mismatched RAM blocks in the precomputation stage. In this work, a complete power analysis of RAM-based CAM using Xilinx Vivado has been performed. The comparison of the power consumption between the conventional scheme and low-power schemes is illustrated. Under the same test case, the average dynamic power consumption of CAM with the pipelining scheme can be reduced by 86% compared to the conventional scheme. The precomputation scheme based on the pipelining scheme further optimizes the power consumption of CAM. It decreases the final result of power estimation by 36% compared to the pipelining scheme. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/7812 | |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | CAM | en_US |
| dc.subject | Content Addressable Memory | en_US |
| dc.subject | FPGA | en_US |
| dc.subject | Power Analysis | en_US |
| dc.subject | pipelining | en_US |
| dc.subject | precomputation | en_US |
| dc.title | Content Addressable Memory (CAM) Implementation and Power Analysis on FPGA | en_US |
| dc.type | project | en_US |