VLSI implementation of digital filters
| dc.contributor.author | Sunder, Sreenivasachar | |
| dc.contributor.supervisor | Antoniou, Andreas | |
| dc.contributor.supervisor | el Guibaly, Fayez H. F. | |
| dc.date.accessioned | 2018-07-03T19:45:23Z | |
| dc.date.available | 2018-07-03T19:45:23Z | |
| dc.date.copyright | 1992 | en_US |
| dc.date.issued | 2018-07-03 | |
| dc.degree.department | Department of Electrical and Computer Engineering | en_US |
| dc.degree.level | Doctor of Philosophy Ph.D. | en_US |
| dc.description.abstract | In this thesis we describe a method of mapping one-dimensional and multidimensional filter algorithms onto systolic architectures using the z-domain approach. In this approach the filter algorithm is first transformed into its corresponding z-domain equivalent and recursive expressions similar to single assignment codes are derived using Horner's rule or other polynomial evaluation techniques. By obtaining different recursive expressions, different systolic structures can be derived. The characteristics of these structures can easily be deduced from the recursive expressions. The multidimensional filters derived are modular and hierarchical, i.e., the three-dimensional structures are obtained from the two-dimensional ones which are in turn obtained from one-dimensional structures. In considering the design of any array processor, it is important to consider the design of the processing elements involved. The most important and demanding operation in these elements is the multiplication. Four different multipliers are designed in which the number of operations required to produce the desired result is reduced. The reduced number of operations along with the advantages of very-large-scale integration technology in terms of increased device density and faster switching make these multipliers potential candidates in high-speed signal processing applications. The first multiplier is an area-efficient multiplier that uses approximately 50% of the area of a full parallel multiplier. In this multiplier only the units yielding the most significant part of the product are used. In addition, a correction unit is incorporated to minimize the error resulting from circumventing the use of units yielding the least significant part of the product. The second multiplier is based on the modified octal Booth algorithm in which four-bit segments of the multiplier are scanned and corresponding operations effected on the multiplicand. The third multiplier is a diminished-1 multiplier that finds application in the Fermat number-theoretic transform. In this multiplier the use of a translator is circumvented and a novel technique for translation is incorporated in the multiplier structure. The fourth multiplier is one that performs an inner-product operation without the use of an accumulator thereby resulting in increased speed and reduced area. Finally we discuss the VLSI implementations of three of the multipliers mentioned above, a second-order digital filter, and a single processing element that can be used as a basic unit in designing one-dimensional and multidimensional digital filters. Some associated problems in digital-filter structure. viz., the quantization and overflow limit-cycle oscillations; have been taken into consideration and ways have been suggested for their elimination. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/9571 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Integrated circuits, very large scale integration | en_US |
| dc.subject | Parallel processing (Electronic computers) | en_US |
| dc.subject | Digital filters (Mathematics) | en_US |
| dc.subject | Signal processing, digital techniques | en_US |
| dc.title | VLSI implementation of digital filters | en_US |
| dc.type | Thesis | en_US |