A fast and area-efficient architecture for classifying images based on binarization and a binary dual-feature set

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dc.contributor.authorAttarmoghaddam, Narges
dc.contributor.supervisorLi, Kin Fun
dc.date.accessioned2022-09-01T22:55:17Z
dc.date.available2022-09-01T22:55:17Z
dc.date.copyright2022en_US
dc.date.issued2022-09-01
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelDoctor of Philosophy Ph.D.en_US
dc.description.abstractImage classification is an active research area in computer vision with many applications. Image classification is a computationally complex task, but for embedded applications, only limited resources are allowed. Moreover, additional constraints such as reliable classification accuracy, high-throughput performance, power-efficiency, and real-time speed must be fulfilled. Due to potential for parallelism, low power consumption, scalable resource utilization, and reconfigurability, Field-Programmable Gate Array (FPGA) devices are well-suited to overcome these challenges in image classification system implementation. In this dissertation, we implemented two feature-based image classification systems using binary feature sets. A binary feature of an image pixel is represented using one bit, while a non-binary feature is represented using more bits. Therefore, implementing an image classification system based on a binary feature set needs fewer hardware resources for storage and computation. The first proposed system is founded on a single binary Histograms of Oriented Gradients (HOG) feature set. Using a binary feature set generally leads to an area-efficient and faster architecture; however, accuracy is lost because binary features contain less information than non-binary features. We, therefore, proposed the second system that uses a dual feature set that combines HOG and Local Binary Pattern (LBP) features to improve classification accuracy performance. The Support Vector Machine (SVM) classification algorithm is utilized as the classifier in both proposed systems. To obtain binary features, two steps of binarization are applied to the HOG descriptor. First, HOG features are extracted from binary images to simplify the feature extraction process. Second, the block histogram normalization of the both HOG and LBP descriptors is replaced using binarization to reduce hardware resource utilization in the descriptors and the SVM classifier. Binary-based computation in the proposed systems results in resource utilization reduction, thus allowing an area-efficient architecture even with two feature descriptors implemented. Compared to similar existing works, our system speeds up the classification process while utilizing fewer hardware resources, with comparable accuracy.en_US
dc.description.scholarlevelGraduateen_US
dc.identifier.bibliographicCitationN. Attarmoghaddam, K. F. Li, (2022) IEEE Transactions on Circuits and Systems II: Express Briefs.en_US
dc.identifier.urihttp://hdl.handle.net/1828/14174
dc.languageEnglisheng
dc.language.isoenen_US
dc.rightsAvailable to the World Wide Weben_US
dc.subjectImage classificationen_US
dc.subjectBinary dual-feature seten_US
dc.subjectSVM classifieren_US
dc.subjectHOG feature descriptoren_US
dc.subjectLBP feature descriptoren_US
dc.subjectArea-efficienten_US
dc.titleA fast and area-efficient architecture for classifying images based on binarization and a binary dual-feature seten_US
dc.typeThesisen_US

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