Extended architectural enhancements for minimizing message delivery latency on cache-less architectures (e.g., Cell BE)

dc.contributor.authorKroeker, Anthony
dc.contributor.supervisorDimopoulos, Nikitas J.
dc.date.accessioned2012-01-12T23:43:09Z
dc.date.available2012-01-12T23:43:09Z
dc.date.copyright2011en_US
dc.date.issued2012-01-12
dc.degree.departmentDept. of Electrical and Computer Engineeringen_US
dc.degree.levelMaster of Applied Science M.A.Sc.en_US
dc.description.abstractThis thesis proposes to reduce the latency of MPI receive operations on cacheless architectures, by removing the delay of copying messages when they are first received. This is achieved by copying the messages directly into buffers in the lowest level of the memory hierarchy (e.g., scratchpad memory). The previously proposed solution introduced an Indirection Cache which would map between the receive variables and the buffered message payload locations. This proved somewhat beneficial, but the lookup penalty of the Indirection Cache limited its effectiveness. Therefore this thesis proposes that a most recently used buffer (i.e., an Indirection Buffer) be placed in front of the Indirection Cache to eliminate this penalty and speed up access. The tests conducted demonstrated that this method was indeed effective and improved over the original method by at least an order of magnitude. Finally, examination of implementation feasibility showed that this could be implemented with a small Cache, and that even with access times 6x slower than initially assumed, the approach with the Indirection Buffer would still be effective.en_US
dc.description.scholarlevelGraduateen_US
dc.identifier.urihttp://hdl.handle.net/1828/3813
dc.languageEnglisheng
dc.language.isoenen_US
dc.rights.tempAvailable to the World Wide Weben_US
dc.subjectcomputer engineeringen_US
dc.subjectcomputer architectureen_US
dc.subjectcell processoren_US
dc.subjectmpien_US
dc.subjectcache injectionen_US
dc.subjectcachelessen_US
dc.subjectIndirection Cacheen_US
dc.subjectIndirection Bufferen_US
dc.titleExtended architectural enhancements for minimizing message delivery latency on cache-less architectures (e.g., Cell BE)en_US
dc.typeThesisen_US

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