A high-level language and CAD environment for BIST embedding
| dc.contributor.author | Byrne, Rodrigue | |
| dc.contributor.supervisor | Miller, D. M. | |
| dc.date.accessioned | 2018-07-12T00:14:04Z | |
| dc.date.available | 2018-07-12T00:14:04Z | |
| dc.date.copyright | 1993 | en_US |
| dc.date.issued | 2018-07-11 | |
| dc.degree.department | Department of Computer Science | en_US |
| dc.degree.level | Doctor of Philosophy Ph.D. | en_US |
| dc.description.abstract | The reliable construction of VLSI integrated circuits (ICs) requires that the ICs be tested after fabrication. An alternative to performing external testing is to create ICs that can test themselves with a built-in self-test (BIST) mode. Unfortunately the problem of embedding a self-test operating mode to the functional design is difficult for two reasons. (1) The creation of test sets that effectively test digital circuits requires the solution of several intractable problems. (2) The hardware resources dedicated to self-test are usually constrained. Modifications to the Logic III hardware description language and a new computer-aided design (CAD) tool, 1g3, are presented in this dissertation as an environment that allows BIST embedding to be created and evaluated. The major premise behind this work is that BIST design can be treated in a similar fashion as functional design, and that the designer can address the constraints of a BIST mode at the same time as the functional constraints. The modified language, called Logic III(UVic), allows BIST embeddings to be specified by an embedding module which describes how the circuit's memory elements are realized. This dissertation presents a library of embedding modules that realize several of the most common BIST architectures. Case studies using this environment are presented for an ALU, CORDIC, GCD, and string matching circuits. A BIST mode with almost 100% single stuck-at fault coverage is realized for each circuit. This shows that the CAD environment can be used to create self-testing circuits. In addition to aiding users in embedding BIST functionality, the 1g3 tool can be used to evaluate specific BIST architectures. Properties of BIST test pattern generators are presented that are used in analyzing the effectiveness of the generators for delay-fault testing. A novel approach based on creating a deterministic finite automaton that recognizes the fault-free responses is presented. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/9680 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Integrated circuits | en_US |
| dc.subject | Embedding theorems | en_US |
| dc.subject | Digital electronics | en_US |
| dc.subject | Computers | en_US |
| dc.subject | Circuits | en_US |
| dc.title | A high-level language and CAD environment for BIST embedding | en_US |
| dc.type | Thesis | en_US |