Fixed-point hardware design for CPWC image reconstruction
| dc.contributor.author | Shi, Ji | |
| dc.contributor.supervisor | Rakhmatov, Daler N. | |
| dc.date.accessioned | 2020-03-28T01:13:12Z | |
| dc.date.available | 2020-03-28T01:13:12Z | |
| dc.date.copyright | 2020 | en_US |
| dc.date.issued | 2020-03-27 | |
| dc.degree.department | Department of Electrical and Computer Engineering | |
| dc.degree.level | Master of Applied Science M.A.Sc. | en_US |
| dc.description.abstract | Coherent plane-wave compounding (CPWC) ultrasonography is an important imaging modality that allows for very high frame rates. During CPWC image reconstruction, computationally expensive delay-and-sum beamforming can be replaced by faster Fourier-domain remapping. The thesis deals with the MATLAB and hardware implementation of one of the recently proposed Fourier-domain CPWC reconstruction methods, namely, plane-wave (PW) Stolt's migration algorithm. We first present the floating- and fixed-point implementations of the said migration algorithm in MATLAB, and then perform quantitative evaluation of the reconstruction results, showing that it is feasible to obtain high-quality compounded images using hardware-oriented scaled fixed-point calculations, as opposed to more expensive software-oriented floating-point arithmetic. We also generate Xilinx FPGA-based implementations of both floating- and fixed-point MATLAB-based algorithms, using a high-level synthesis (HLS) design flow that collaboratively employs MATLAB Coder and Vivado HLS tool. MATLAB Coder can automatically convert a MATLAB code into a C program, while Vivado HLS can convert the resulting C program into a synthesizable Verilog/VHDL description. Results show that our fixed-point FPGA implementation is more resource and power efficient and can also operate at a higher clock frequency compared to its floating-point counterpart. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.bibliographicCitation | J. Shi and D. Rakhmatov,“Fixed-point CPWC ultrasound image reconstruction,”in 2019 IEEE International Ultrasonics Symposium (IUS). IEEE, 2019, pp. 1282–1285. | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/11658 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Plane-wave ultrasound imaging | en_US |
| dc.subject | Fixed-point computation | en_US |
| dc.subject | FPGA implementation | en_US |
| dc.title | Fixed-point hardware design for CPWC image reconstruction | en_US |
| dc.type | Thesis | en_US |