VLSI design of a testable processor array for feature extraction
Date
1988
Authors
Aubry, Patrice P.
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Abstract
A VLSI CMOS design performing feature extraction for machine and handwritten printed character recognition is described. The chip is designed to efficiently process a character in the form of a two-dimensional binary image. Although the algorithm for the character recognition and its architectural configuration are presented, the processor array necessary for feature extraction is dealt with in detail. Built-In-Self-Test (BIST) is incorporated in each unit cell to enable exhaustive testing. Fault tolerance is allowed for scattered faulty cells. The array is considered faulty if clustered faulty cells are detected. Simulation results and hardware details are presented. Finally, future considerations and applications are discussed.