VLSI design of a testable processor array for feature extraction

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dc.contributor.authorAubry, Patrice P.en_US
dc.date.accessioned2024-08-12T19:31:13Z
dc.date.available2024-08-12T19:31:13Z
dc.date.copyright1988en_US
dc.date.issued1988
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en
dc.description.abstractA VLSI CMOS design performing feature extraction for machine and hand­written printed character recognition is described. The chip is designed to efficiently process a character in the form of a two-dimensional binary im­age. Although the algorithm for the character recognition and its architec­tural configuration are presented, the processor array necessary for feature extraction is dealt with in detail. Built-In-Self-Test (BIST) is incorporated in each unit cell to enable exhaustive testing. Fault tolerance is allowed for scattered faulty cells. The array is considered faulty if clustered faulty cells are detected. Simulation results and hardware details are presented. Finally, future considerations and applications are discussed.
dc.format.extent103 pages
dc.identifier.urihttps://hdl.handle.net/1828/16997
dc.rightsAvailable to the World Wide Weben_US
dc.titleVLSI design of a testable processor array for feature extractionen_US
dc.typeThesisen_US

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