VHDL Implementation of PPR Systolic Array Architecture for Polynomial GF(2^m) Multiplication

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dc.contributor.authorNia, Ali
dc.contributor.supervisorGebali, Fayez
dc.date.accessioned2013-04-30T21:36:15Z
dc.date.available2013-04-30T21:36:15Z
dc.date.copyright2013en_US
dc.date.issued2013-04-30
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en_US
dc.description.abstractThis thesis is devoted to efficient VHDL design of Systolic Array Architecture for Polynomial GF(2^m) multiplication. The hardware implements the Processor Elements(PE) and Systolic Array design for Progressive Product Reduction (PPR) method proposed by Gebali and Atef. The experiment first implements a simpler irreducible polynomials GF(2^5) based on the defined algorithms for PPR in order to confirm the functionality of the design and then tries the bigger value of m for GF(2^133) and GF(2^233), recommended by NIST. The thesis is comparing the three designs based on their power consumption, Maximum Data path delay and device utilization. It also looking in to the different optimization method for the designs and recommends a design optimization based on circuit modification.en_US
dc.description.proquestcode0544en_US
dc.description.proquestemailalinia@uvic.caen_US
dc.description.scholarlevelGraduateen_US
dc.identifier.urihttp://hdl.handle.net/1828/4575
dc.languageEnglisheng
dc.language.isoenen_US
dc.rights.tempAvailable to the World Wide Weben_US
dc.subjectGalois Field(2m)en_US
dc.subjectmultiplicationen_US
dc.subjectProgressive product reductionen_US
dc.titleVHDL Implementation of PPR Systolic Array Architecture for Polynomial GF(2^m) Multiplicationen_US
dc.typeThesisen_US

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