Evaluation in built-in self-test
| dc.contributor.author | Zhang, Shujian | |
| dc.contributor.supervisor | Miller, D. M. | |
| dc.contributor.supervisor | Muzio, Jon C. | |
| dc.date.accessioned | 2017-08-21T21:12:30Z | |
| dc.date.available | 2017-08-21T21:12:30Z | |
| dc.date.copyright | 1998 | en_US |
| dc.date.issued | 2017-08-21 | |
| dc.degree.department | Department of Computer Science | en_US |
| dc.degree.level | Doctor of Philosophy Ph.D. | en_US |
| dc.description.abstract | This dissertation addresses two major issues associated with a built-in self-test environment: (1) how to measure whether a given test vector generator is suitable for testing faults with sequential behavior, and (2) how to measure the safety of self-checking circuits. Measuring the two-vector transition capability for a given test vector generator is a key to the selection of the generators for stimulating sequential faults. The dissertation studies general properties for the transitions and presents a novel, comprehensive analysis for the linear feedback shift registers and the linear hybrid cellular automata. As a result, the analysis solves the open problem as to “how to properly separate the inputs when the LHCA-based generator is used for detecting delay faults”. In general, a self-checking circuit has additional hardware redundancy than the original circuit and as a result, the self-checking circuit may have a higher failure rate than the original one. The dissertation proposes a fail-safe evaluation to predict the probability of the circuit not being in the fail-state. Compared with existing evaluation methods, the fail-safe evaluation is more practical because it estimates the safety of the circuit, which is decreasing as time goes on, instead of giving a constant probability measure. Various other results about improving fault coverage for transition delay faults and testing in macro-based combinational circuits are derived as well. | en_US |
| dc.description.scholarlevel | Graduate | en_US |
| dc.identifier.uri | http://hdl.handle.net/1828/8440 | |
| dc.language | English | eng |
| dc.language.iso | en | en_US |
| dc.rights | Available to the World Wide Web | en_US |
| dc.subject | Generators (Computer programs) | en_US |
| dc.subject | Sequential processing (Computer science) | en_US |
| dc.title | Evaluation in built-in self-test | en_US |
| dc.type | Thesis | en_US |