Reconfigurable co-design of a computationally intensive mathematical problem
Date
2010-02-26T18:02:21Z
Authors
Iaderoza, Beatriz Chiavegatto
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Abstract
A reprogrammable hardware platform is used for the Co-design and implementation of a computationally intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)). The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software Co-design methodologies and techniques, and it is designed, implemented and evaluated on two distinct platforms, not simply by simulations. FPGAs are used as part of the reconfigurable hardware in both a PCI-based environment and in a more successful System-on-Chip (SOC) platform, which takes advantage of the closely-coupled interconnection between the hardware and software, thus minimizing the communication overhead. The case study, findings and general analysis lead to a possible ideal architecture for future approaches. Moreover, a more general detailed strategy can be seen for the transformation from software to a Co-design paradigm, maximizing parallelism.
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Keywords
embedded computer systems, system design