Reconfigurable co-design of a computationally intensive mathematical problem
| dc.contributor.author | Iaderoza, Beatriz Chiavegatto | |
| dc.contributor.supervisor | Serra, Micaela | |
| dc.date.accessioned | 2010-02-26T18:02:21Z | |
| dc.date.available | 2010-02-26T18:02:21Z | |
| dc.date.copyright | 2006 | en |
| dc.date.issued | 2010-02-26T18:02:21Z | |
| dc.degree.department | Department of Computer Science | |
| dc.degree.level | Master of Science M.Sc. | en |
| dc.description.abstract | A reprogrammable hardware platform is used for the Co-design and implementation of a computationally intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)). The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software Co-design methodologies and techniques, and it is designed, implemented and evaluated on two distinct platforms, not simply by simulations. FPGAs are used as part of the reconfigurable hardware in both a PCI-based environment and in a more successful System-on-Chip (SOC) platform, which takes advantage of the closely-coupled interconnection between the hardware and software, thus minimizing the communication overhead. The case study, findings and general analysis lead to a possible ideal architecture for future approaches. Moreover, a more general detailed strategy can be seen for the transformation from software to a Co-design paradigm, maximizing parallelism. | en |
| dc.identifier.uri | http://hdl.handle.net/1828/2277 | |
| dc.language | English | eng |
| dc.language.iso | en | en |
| dc.rights | Available to the World Wide Web | en |
| dc.subject | embedded computer systems | en |
| dc.subject | system design | en |
| dc.subject.lcsh | UVic Subject Index::Sciences and Engineering::Applied Sciences::Computer science | en |
| dc.title | Reconfigurable co-design of a computationally intensive mathematical problem | en |
| dc.type | Thesis | en |