Implementation of Binary and Ternary Convolutional Codes on an FPGA

dc.contributor.author	Madela, Bharath Rao
dc.contributor.supervisor	Gulliver, T. Aaron
dc.date.accessioned	2021-09-15T04:53:31Z
dc.date.available	2021-09-15T04:53:31Z
dc.date.copyright	2021	en_US
dc.date.issued	2021-09-14
dc.degree.department	Department of Electrical and Computer Engineering
dc.degree.level	Master of Engineering M.Eng.	en_US
dc.description.abstract	In modern wireless communication systems, the channels are corrupted by noise and interference. To address this issue, error control coding is employed to reliably transfer data. Convolutional codes are widely employed as they are easy to encode and decode. The focus of this work is the implementation of binary and ternary convolutional codes on an FPGA. As most data is binary, binary to ternary conversion is employed to implement ternary convolutional codes on an FPGA which is a binary device. The design architecture for both types of codes is discussed and comparisons are made based on structure, data rate, speed and resource utilization.	en_US
dc.description.scholarlevel	Graduate	en_US
dc.identifier.uri	http://hdl.handle.net/1828/13392
dc.language.iso	en	en_US
dc.rights	Available to the World Wide Web	en_US
dc.subject	FPGA	en_US
dc.subject	Convolutional	en_US
dc.subject	code	en_US
dc.subject	FEC	en_US
dc.subject	error correction	en_US
dc.subject	binary	en_US
dc.subject	ternary	en_US
dc.title	Implementation of Binary and Ternary Convolutional Codes on an FPGA	en_US
dc.type	project	en_US

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Description:: MEng Project report on topic "Implementation of Binary and Ternary Convolutional Codes on an FPGA"

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