Word-serial unified and scalable semi-systolic processor for field multiplication and squaring
| dc.contributor.author | Ibrahim, Atef | |
| dc.date.accessioned | 2021-01-26T20:41:49Z | |
| dc.date.available | 2021-01-26T20:41:49Z | |
| dc.date.copyright | 2021 | en_US |
| dc.date.issued | 2021 | |
| dc.description.abstract | This paper exhibits a word-serial unified and scalable semi-systolic processor core for concurrently executing both multiplication and squaring operations over GF(). The processor is extracted by applying a chosen non-linear scheduling and projection functions to the dependency graph of the adopted bipartite multiplication-squaring algorithm. It has the advantage of sharing the data-path resources between the two operations leading to considerable savings in both space and power resources. Also, the processor’s scalability nature provides the designer with higher flexibility to manage the processor size as well as its execution time. The acquired ASIC synthesis results of the explored word-serial multiplier-squarer architecture and the reported competing word-serial multiplier architectures indicate that the developed design significantly outperforms the competing ones in terms of area and consumed energy at the word-size of 32-bits. Therefore, the explored architecture is more suited for realizing cryptographic primitives in all resource-constrained embedded applications operating at this word-size. | en_US |
| dc.description.reviewstatus | Reviewed | en_US |
| dc.description.scholarlevel | Faculty | en_US |
| dc.description.sponsorship | The author would like to acknowledge the support of the Deanship of Scientific Research at Prince Sattam Bin Abdulaziz university under the research project # 2020/01/16466. | en_US |
| dc.identifier.citation | Ibrahim, A. (2021). Word-serial unified and scalable semi-systolic processor for field multiplication and squaring. Alexandria Engineering Journal, 60(1), 1379- 1388. https://doi.org/10.1016/j.aej.2020.10.058. | en_US |
| dc.identifier.uri | https://doi.org/10.1016/j.aej.2020.10.058 | |
| dc.identifier.uri | http://hdl.handle.net/1828/12600 | |
| dc.language.iso | en | en_US |
| dc.publisher | Alexandria Engineering Journal | en_US |
| dc.subject | Word-serial systolic/semi-systolic arrays | |
| dc.subject | Cryptographic processors | |
| dc.subject | Finite-field arithmetic | |
| dc.subject | Resource-constrained embedded applications | |
| dc.subject | Hardware security | |
| dc.subject.department | Department of Electrical and Computer Engineering | |
| dc.title | Word-serial unified and scalable semi-systolic processor for field multiplication and squaring | en_US |
| dc.type | Article | en_US |