Parallel and serial concatenated single parity check product codes

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dc.contributor.authorRankin, David M.
dc.contributor.authorGulliver, Thomas Aaron
dc.contributor.authorTaylor, Desmond P.
dc.date.accessioned2014-07-28T21:25:48Z
dc.date.available2014-07-28T21:25:48Z
dc.date.copyright2005en_US
dc.date.issued2005
dc.descriptionSpringerOpenen_US
dc.description.abstractThe parallel and serial concatenation of codes is well established as a practical means of achieving excellent performance. In this paper, we introduce the parallel and serial concatenation of single parity check (SPC) product codes. The weight distribution of these codes is analyzed and the performance is bounded. Simulation results confirm these bounds at high signal-to-noise ratios. The performance of these codes (and some variants) is shown to be quite good given the low decoding complexity and reasonably short blocklengths.en_US
dc.description.reviewstatusRevieweden_US
dc.description.scholarlevelFacultyen_US
dc.identifier.citationD.M. Rankin, T.A. Gulliver and D.P. Taylor. Parallel and Serial Concatenated Single Parity Check Product Codes. EURASIP Journal on Applied Signal Processing 2005:6, 775–783en_US
dc.identifier.urihttp://asp.eurasipjournals.com/content/2005/6/183140
dc.identifier.urihttp://hdl.handle.net/1828/5487
dc.language.isoenen_US
dc.publisherHindawi Publishing Corporationen_US
dc.subjectparallel and serial concatenation
dc.subjectsingle parity check product codes
dc.subject.departmentDepartment of Electrical and Computer Engineering
dc.titleParallel and serial concatenated single parity check product codesen_US
dc.typeArticleen_US

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