A new fault model and its application in synthesizing Toffoli networks




Zhong, Jing

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Reversible logic computing is a rapidly developing research area. Both reversible logic synthesis and testing reversible logic circuits are very important issues in this area. In this thesis, we present our work in these two aspects. We consider a new fault model, namely the crosspoint fault, for reversible circuits. The effects of this kind of fault on the behaviour of the circuits are studied. A randomized test pattern generation algorithm targeting this kind of fault is introduced and analyzed. The relationship between the crosspoint faults and stuck-at faults is also investigated. The crosspoint fault model is then studied for possible applications in reversible logic synthesis. One type of redundancy exists in Toffoli networks in the form of undetectable multiple crosspoint faults. So redundant circuits can be simplified by deleting those undetectable faults. The testability of multiple crosspoint faults is analyzed in detail. Several important properties are proved and integrated into the simplifying algorithm so as to speed up the process. We also provide an optimized implementation of a Reed-Muller spectra based reversible logic synthesis algorithm. This new implementation uses a compact form of the Reed-Muller spectra table of the specified reversible function to save memory during execution. Experimental results are presented to illustrate the significant improvement of this new implementation.



Reversible logic, testing, synthesis, ATPG, fault model, crosspoint fault