Digital bit synchronization of hard limited binary data

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dc.contributor.authorOgmundson, Patrick Gerarden_US
dc.date.accessioned2024-08-15T16:36:58Z
dc.date.available2024-08-15T16:36:58Z
dc.date.copyright1988en_US
dc.date.issued1988
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en
dc.description.abstractThree new digital bit synchronization techniques are presented. Each synchronizer uses a hard limiter to interface between the received analog data waveform and the digital synchronizer. The optimum maximum likelihood synchronizers ( data aided and non data aided) for hard limited data signals are developed. Linear approxima­tions are made to these optimum synchronizers to simplify implementation. The lower bound on the timing error variance of the hard limited data aided synchronizer is established. A zero crossing tracking digital phase locked loop (PLL) suitable for bandlimited data transmission systems is proposed. Pattern jitter (self noise) is reduced by a pattern jitter compensation signal in the PLL feed­back, thus eliminating the need for a prefilter. The timing jitter variance analysis is shown to be an improvement over a previous result for a zero crossing tracking PLL. Computer simulations and laboratory experiments verify the performance of the pattern jitter compensation technique. A PLL synchronizer with a simple adaptive bandwidth control is shown to yield a better acquisition/tracking performance tradeoff than a fixed bandwidth PLL. The adaptive bandwidth control operates by monitoring the location of zero crossings measured at the output of a phase detec­tor. Computer simulation and experimental results for some typical PLL parameters are presented.
dc.format.extent200 pages
dc.identifier.urihttps://hdl.handle.net/1828/19187
dc.rightsAvailable to the World Wide Weben_US
dc.titleDigital bit synchronization of hard limited binary dataen_US
dc.typeThesisen_US

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