The application of current mode circuits in the design of an A/D converter

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dc.contributor.authorLi, Minghongen_US
dc.date.accessioned2024-08-14T21:06:01Z
dc.date.available2024-08-14T21:06:01Z
dc.date.copyright1997en_US
dc.date.issued1997
dc.degree.departmentDepartment of Electrical and Computer Engineering
dc.degree.levelMaster of Applied Science M.A.Sc.en
dc.description.abstractWith the fast development of telecommunications, more and more VLSI chips are required to have small size, low power supply and wide dynamic range. Systems which include analog and digital circuits can be integrated on the same chip using the standard digital CMOS technology. Voltage mode circuits face the problems both in economic and technique. Current mode technique attracts researchers' attention because of its advan­tages over the voltage mode technique. The research in this thesis can be divided into two parts. The first part is on the study of one of the basic building blocks in current mode technique, namely, the dynamic cur­rent mirror. The second part is on the analysis and design of a pipeline stage used in an 8-bit current mode AID converter. The research on the dynamic current mirror primarily focused on error analysis, as well as circuit design. Several methods to reduce the errors are presented. Regulated-cas­cade dynamic current mirror is adopted in this work. An 8-bit current mode AID converter is based on multistage and pipeline architec­ture. Each stage completes one 2-bit conversion. Because of this structure, the speed of the circuit is increased. Since the circuit in each stage is the same, a module has been designed and used for every stage. The research on the pipeline stage begins with the analysis and design of subsystem circuit blocks. Some of them are based on another current mode cir­cuit - adaptive bias cascade current miITor. Each circuit block in the pipeline stage was simulated using Spectre within Cadence graphics. One channel of the converter was simu­lated and it is capable of 8-bit resolution and 355 kHz conversion rate. If 7 parallel chan­nels are used, the sampling rate can be increased to 2.5 MHz.
dc.format.extent141 pages
dc.identifier.urihttps://hdl.handle.net/1828/18689
dc.rightsAvailable to the World Wide Weben_US
dc.titleThe application of current mode circuits in the design of an A/D converteren_US
dc.typeThesisen_US

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